The present invention generally relates to controlling a semiconductor development process, and in particular to a system and method for developer endpoint detection by real-time feed forward control based on scatterometry and/or reflectometry analysis of in-situ grating measurements.
In the semiconductor industry, device densities continue to increase and thus, there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to scale down device dimensions (e.g., width and spacing of interconnecting lines, spacing and diameter of contact holes, surface geometry, such as corners and edges) of various features, more precise control of fabrication processes (e.g., development) are required. The dimensions of and between features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities through scaled down device dimensions.
Conventional development monitoring systems have either lacked feedback control systems, requiring pre-calculated development steps, have had indirect feedback control, which is based on indirect information or have required sacrificing valuable wafer space for destructive testing. Such pre-determined calculations, indirect feedback and/or destructive testing based control do not provide adequate monitoring and thus do not facilitate precise control over the development process. Another conventional form of development control is performed by reproducing development times. But such time based control does not account for wafer to wafer variations and does not account for wafers with various feature densities. Monitoring tools employed in conjunction with metrology based feed-forward information are known in the art and provide improvements over time based control. But such metrology feed-forward systems can be improved by more accurate monitoring, better CD recognition and more precise feed-forward information.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically includes more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Each step can affect the CDs on the ICs. Generally, the manufacturing process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. The size, shape and isolation of such electrically active regions, and thus the reliability and performance of integrated circuits employing such regions thus depend, at least in part, on the precision with which patterns can be developed on a wafer, and the resulting precision with which features beneath such developed patterns can be formed. Unfortunately, commonly used developing and resist processing fabrication systems check for CDs near or at the end of fabrication, or at pre-scheduled time intervals. These types of end-point and interval detection methods can be problematic for several reasons. For example, at late stages in the development process, the presence of at least one over-developed portion of a pattern may render the whole semiconductor device unusable, forcing it to be discarded. In addition, post-fabrication detection/quality control data do not provide a user with real-time information related to the device being fabricated, and thus opportunities to manipulate a development process before it results in a malformed wafer are lost. Post-fabrication data may only allow an estimation or a projection as to what adjustments are needed to correct the development process. Such estimations and/or projections concerning necessary adjustments may lead to continued or recurring fabrication errors. Moreover, such a lengthy adjustment process may cause subsequent fabricated wafers to be wasted in the hopes of mitigating development errors.
Visual inspection methods have been important in the development stages of integrated circuit manufacture. Visually inspecting developed photoresist patterns from a dose-focus matrix is well-known in the art. While visual inspection techniques may be simple to implement, they are difficult to automate, and do not provide in-situ opportunities for process manipulation. Further, visual techniques employing scanning electron microscopes (SEM) and atomic force microscopes (AFM) can be expensive, time-consuming and/or destructive.
Due to the extremely fine patterns that are exposed on a photo resist, controlling the developing process, whereby patterns are developed and hardened over oxide and/or other conductive or insulating layers, is a significant factor in achieving desired critical dimensions. A resist is a thin layer that is coated onto a substrate. The resist is hardened and selectively removed from selected areas after exposure by development. Achieving greater precision in development processes can result, for example, in more precise pattern reproduction which in turn facilitates achieving more precise CDs (e.g., desired lengths and widths between layers, between features and within features). Thus, an efficient system, and/or method, to monitor and control development processes is desired to facilitate manufacturing ICs exhibiting desired critical dimensions.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system and method for directly measuring critical dimensions (CDs) in-situ as they evolve during a development process and for feeding forward control information based on scatterometry and/or reflectometry analysis of such direct measurements so that the development process can be terminated when desired development has occurred. Scatterometry is concerned with the analysis of light reflected and/or refracted at various angles and reflectometry measures the intensity and polarization properties of specularly reflected light. Properties of the reflected, scattered and/or refracted light can be directly correlated to parameters including, the thickness of grating lines and the like. Thus, the present invention, through such real-time scatterometry and/or reflectometry analysis facilitates more accurate CD control from wafer to wafer than is possible through conventional methods and facilitates manipulating (e.g., terminating) a development process.
In accordance with one aspect of the present invention, a test grating similar to the product pattern is formed on the wafer, and thus, during the development process, the test grating can be probed by a scatterometry beam and/or reflectometry beam. The light reflected and/or refracted from the test grating can be employed to extract CD and evolving profile information. In the development process, a puddle of developing material forms on the surface of a wafer. To facilitate probing the test grating, the wafer, which may be located in a spin track, may be spun down so that the puddle of developing material will be static during the beam probe. Once the development process has proceeded to a point where the grating is opened, then CDs from the test grating and reconstructed profile measurements can be analyzed to determine whether an acceptable development process has occurred. If target CDs are not achieved, then the wafer may be marked for reworking and/or discarded.
In accordance with another aspect of the present invention, a system for monitoring and regulating a development process is provided. The system includes a development component that can adapt development parameters (e.g., time, temperature, formula, concentration) associated with developing a photoresist on a wafer and a development component driving system for driving the development component. The system further includes a system for directing light toward a grating located on the wafer, a development monitoring system operable to measure development progress (e.g., under-developed, over-developed, acceptably developed) from light reflected from the grating and a processor coupled to the development monitoring system and the development component driving system. The processor receives development progress data from the measuring system and analyzes the development progress data by comparing the development progress data to stored development data to generate feed-forward control data that can be employed to control the development component, including terminating the development process. In one example of the present invention, the development monitoring system further includes a scatterometry system and/or a reflectometry system for processing the light reflected from the gratings.
Another aspect of the present invention provides a method for monitoring and regulating a development process. The method includes logically partitioning a wafer into portions, fabricating gratings on the wafer, directing an incident light onto the gratings, collecting a reflected light reflected from the gratings, measuring the reflected light to determine CDs associated with the grating, computing adjustments, including terminating instructions, for development components by comparing the CDs to scatterometry and/or reflectometry signatures associated with stored CDs and adjusting the development process based, at least in part, on the computed adjustments.
To the accomplishment of the foregoing and related ends, certain illustrative aspects of the invention are described herein in connection with the following description and the annexed drawings. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such aspects and their equivalents. Other advantages and novel features of the invention may become apparent from the following detailed description of the invention when considered in conjunction with the drawings.